Modern memory devices, such as dynamic random access memories (DRAMs), often include an internal voltage regulator to derive a regulated internal supply voltage from an external supply voltage. This internal supply voltage is typically provided to the memory device's memory cell array and to the array's peripheral control circuits on a common power bus.
This typical voltage regulation system can be problematic for three reasons. First, the common power bus can be very long in a modern memory device. As a result, localized variations in the internal supply voltage along the bus can go unregulated by the internal voltage regulator. Second, sudden current draws from the common power bus by the memory cell array at the beginning of active cycles of the memory device can produce noise in the internal supply voltage which can affect operation of the array's peripheral control circuits. Third, the typical internal voltage regulator uses power relatively inefficiently.
Therefore, there is a need in the art for a memory device with a voltage regulation system which provides responsive regulation of the internal supply voltage along the entire length of the power bus. The system should also reduce the effect noise from the memory cell array has on operation of the array's peripheral control circuits, and it should use power more efficiently.